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| QUINT EXCLUSIVE OR/NOR GATE FEATURES s Max. propagation delay of 1000ps s IEE min. of -58mA s Extended supply voltage option: VEE = -4.2V to -5.5V s Voltage and temperature compensation for improved noise immunity s Internal 75K input pull-down resistors s 50% faster than Fairchild 300K at lower power s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages SY100S307 DESCRIPTION The SY100S307 is an ultra-fast quint exclusive-OR/ NOR gate designed for use in high-performance ECL systems. A function output that is the wire-OR result of the exclusive-OR outputs is also available. The inputs on the device have 75K pull-down resistors. PIN CONFIGURATIONS D1a Oa VEES D2a Oa Ob Ob 4 3 2 1 28 27 26 19 20 21 22 23 24 25 11 10 9 8 7 6 5 D1b D2b VEE VEES D1c D2c D2d 12 13 14 15 16 17 18 Oc Oc VCCA VCC VCC F Od Top View PLCC J28-1 BLOCK DIAGRAM F D1a D2a D1b D2b D1c D2c D1d D2d D1e D2e Oa Oa Ob Ob Oc Oc Od Od Oe Oe D1e D2e VEES Oe Oe D1d Od D2d D2c D1c VEE D2b 1 2 3 4 5 6 D1d D1e D2e Oe Oe Od 24 23 22 21 20 19 18 17 Top View 16 Flatpack 15 F24-1 14 13 7 8 9 10 11 12 D1b D2a D1a Oa Oa Ob Ob F VCC VCCA PIN NAMES Pin Dna - Dne E Oa - Oe Oa - Oe VEES VCCA Function Data Inputs (n-1...5) Enable Input Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs Od Rev.: G Oc Oc Amendment: /0 1 Issue Date: July, 1999 Micrel SY100S307 LOGIC EQUATION F = (D1a D2a) + (D1b D2b) + (D1c D2c) + (D1d D2d) + (D1e D2e). DC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND Symbol IIH Parameter Input HIGH Current D2a -- D2e D2a -- D2e Power Supply Current Min. -- -- -58 Typ. -- -- -40 Max. 200 250 -27 mA Inputs Open Unit A Condition VIN = VIH (Max.) IEE AC ELECTRICAL CHARACTERISTICS CERPACK VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND TA = 0C Symbol tPLH tPH2 tPLH tPHL tPLH tPHL tTLH tTHL Parameter Propagation Delay D2a -- D2e to O, O Propagation Delay D1a -- D1e to O, O Propagation Delay Data to F Transition Time 20% to 80%, 80% to 20% Min. 200 200 300 300 Max. 1100 1000 1525 900 TA = +25C Min. 200 200 300 300 Max. 1150 950 1525 900 TA = +85C Min. 200 200 300 300 Max. 1100 1000 1525 900 Unit ps ps ps ps Condition PLCC VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND TA = 0C Symbol tPLH tPH2 tPLH tPHL tPLH tPHL tTLH tTHL Parameter Propagation Delay D2a -- D2e to O, O Propagation Delay D1a -- D1e to O, O Propagation Delay Data to F Transition Time 3 20% to 80%, 80% to 20% Min. 300 300 300 00 Max. 1000 900 1425 900 TA = +25C Min. 300 300 300 300 Max. 1000 900 1425 900 TA = +85C Min. 300 300 300 300 Max. 1000 930 1425 900 Unit ps ps ps ps Condition 2 Micrel SY100S307 TIMING DIAGRAM 0.7 0.1 ns INPUT 80% 50% 20% -1.69V TRUE tPHL tPLH 0.7 0.1 ns -0.95V 50% OUTPUT tPLH tPHL 80% 50% 20% tTLH tTHL COMPLEMENT Propagation Delay and Transition Times NOTE: VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND PRODUCT ORDERING CODE Ordering Code SY100S307FC SY100S307JC SY100S307JCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial 3 Micrel SY100S307 24 LEAD CERPACK (F24-1) Rev. 03 4 Micrel SY100S307 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 5 |
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